PCA9575HF,118

The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the NXP family of I²C-bus I/O expanders. The improvements include lower supply current, lower operating voltage of 1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 16 I/O ports can be configured as an input or output independent of each other and default on start-up to inputs. I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum; for example in battery powered mobile applications and clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. PCA9575 has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/Os is required. The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or pull-down feature for I/Os is also provided. The output stage consists of two banks each of 8-bit configuration registers, input registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down registers and polarity inversion registers. These registers allow the system master to program and configure 16 GPIOs through the I²C-bus. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read registers can

• Separate supply rails for core logic and each of the two I/O banks provides voltage level shifting
• 1.1 V to 3.6 V operation with level shifting feature
• Very low standby current: < 2 µA
• 16 configurable I/O pins organized as 2 banks that default to inputs at power-up
• Outputs:
  • Totem pole: 1 mA source and 3 mA sink
  • Independently programmable 100 kO pull-up or pull-down for each I/O pin
  • Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs
• Inputs:
  • Programmable bus hold provides valid logic level when inputs are not actively driven
  • Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up
  • Polarity Inversion register allows inversion of the polarity of the I/O pins when read
• 400 kHz I²C-bus serial