PCA9512AD,118

The PCA9512A/B is a hot swappable I²C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512A/B provides bidirectional buffering, keeping the backplane and card capacitances isolated. The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital input pin that enables and disables the rise time accelerators on all four SDAn and SCLn pins. During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip. The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allows them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in parallel and to the I²C compliant side of static offset bus buffers, but not to the static offset side of those bus buffers.

• Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems
• Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards
• Built-in ?V/?t rise time accelerators on all SDA and SCL lines (0.6 V threshold) with ability to disable ?V/?t rise time accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (V_CC or V_CC2) to be the same
• 5 V to 3.3 V level translation with optimum noise margin
• High-impedance SDAn and SCLn pins for V_CC or V_CC2 = 0 V
• 1 V precharge on all SDAn and SCLn pins
• Supports clock stretching and multiple master arbitration and synchronization
• Operating power supply voltage range: 2.7 V to 5.5 V
• 0 Hz to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per