MPC5554MZP132

MPC5554MZP132 is a MPC5500 family of microcontrollers built on the Power Architecture embedded technology. The MPC5554 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB) unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data. The complex input/output timer functions of the MPC5554 are performed by two enhanced time processor unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language.

• 132MHz frequency
• Fully specification qualified
• PBGA-416 package
• Temperature range from –40° C to 125° C
• On-chip enhanced queued dual analogue-to-digital converter
• System integration unit (SIU) performs several chip-wide configuration functions