MPC5125YVN400
32 Bit Microcontroller, mobileGT, MPC5 Family MPC51xx Series Microcontrollers, Power Architecture
- RoHS 10 Compliant
- Tariff Charges
The MPC5125YVN400 is a 32-bit Microcontroller based on high performance e300 CPU core operates at a maximum frequency of 400MHz. The e300 CPU core is based on the power architecture technology with a rich set of peripheral functions focused on communications and systems integration. The device incorporates 32kB on-chip SRAM and peripherals like controller area network (CAN) modules, 10/100Base Ethernet USB 2.0 OTG controller with ULPI interface and 64 general-purpose I/O pins.
- Low power design
- Display interface unit (DIU)
- DDR1, DDR2, low-power mobile DDR (LPDDR) and 1.8V/3.3V SDR DRAM memory controllers
- DMA subsystem
- Flexible multi-function external memory bus (EMB) interface
- NAND flash controller (NFC)
- LocalPlus interface (LPC)
- MMC/SD/SDIO card host controller (SDHC)
- Programmable serial controller (PSC)
- Inter-Integrated Circuit (I2C) communication interfaces
Technical Attributes
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| Description | Value | |
|---|---|---|
| 32-bit Bit | ||
| e300 Power Architecture | ||
| TEBGA | ||
| Surface Mount | ||
| CAN, Ethernet, I2C, SPI, UART, USB | ||
| MPC5 | ||
| MPC51xx | ||
| 64 | ||
| 324 | ||
| 400 MHz | ||
| 85 °C | ||
| -40 °C | ||
| MPC5 Family MPC51xx Series Microcontrollers | ||
| 32 KB | ||
| 1.47, 1.9 V | ||
| 1.33, 1.7 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.A.2 |
| HTSN: | 8542310025 |
| Schedule B: | 8542310075 |