LPC3220FET296/01,5

The LPC3220 operates at CPU frequencies of up to 266 MHz. The NXP implementation uses an ARM926EJ-S CPU core with a Harvard architectur, 5-stage pipeline, and an integral Memory Management Unit (MMU). The LPC3220 also includes 128 kB of on-chip static RAM, a NAND flash interface, and an external bus interface that supports SDR and DDR SDRAM, as well as static devices. In addition, the LPC3220 includes a USB 2.0 full-speed interface, seven UARTs, two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single output PWMs, a motor control PWM, six general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option.

• ARM926EJS processor, running at CPU clock speeds up to 266 MHz
• Vector Floating Point (VFP) coprocessor
• 32 kB instruction cache and a 32 kB data cache
• Up to 128 kB of Internal SRAM (IRAM)
• Selectable boot-up from various external devices
• Multi-layer AHB system that provides a separate bus for each AHB master
• External memory controller for DDR and SDR SDRAM as well as for static devices
• Two NAND flash controllers
• Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC)
• Eight channel General Purpose DMA (GPDMA) controller on the AHB
• USB interface supporting either device, host (OHCI compliant), or On-The-Go
• Four standard UARTs with fractional baud rate generation
• Three additional high-speed UARTs intended for on-board communications
• Two SPI controllers
• Two SSP controllers
• Two I2C-bus interfaces with standard open-drain pins
• Two I2S-bus i