LPC11E37HFBD64/4QL

The LPC11E3x are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11E3x operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC11E3x includes up to 128 kB of flash memory, up to 12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up to 54 general purpose I/O pins. The I/O Handler is a software library-supported hardware engine that can be used to add performance, connectivity and flexibility to system designs. It is available on the LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART, I 2C, and I2S with no or very low additional CPU load and can off-load the CPU by performing processing-intensive functions like DMA transfers in hardware.

• System:
  • ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
  • ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
  • Non Maskable Interrupt (NMI) input selectable from several input sources.
  • System tick timer.
• Memory:
  • Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase (256 byte) access.
  • 4 kB on-chip EEPROM data memory; byte erasable and byte programmable; on-chip API support.
  • 12 kB SRAM data memory.
  • 16 kB boot ROM.
  • In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
  • ROM-based 32-bit integer division routines.
• Debug options:
  • Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan Description Language).
  • Serial Wire Debug.