DSP56F805FV80E

The DSP56F805FV80E is a 16-bit Digital Signal Controller combines the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals on a single chip. The 56800 core is based on a Harvard-style architecture consisting of three execution units which operate in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP-and MCU-style applications. The instruction set is also highly efficient for C compilers, enabling rapid development of optimized control applications. The 56F805 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F805 also provides two external dedicated interrupt lines and up to 32 general purpose input/output (GPIO) lines, depending on peripheral configuration.

• Single-cycle 16 x 16-bit parallel multiplier-accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support