HEF4027BT,653
Flip Flop, HEF4027, JK, 60 ns, 30 MHz, 3 mA, 16 Pins, SOIC
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RoHS 10 Compliant -
Tariff Charges
The HEF4027BT is a dual JK Flip-flop features independent set-direct (SD), clear-direct (CD), clock inputs and outputs (Q, Q\). Data is accepted when clock is low and transferred to the output on the positive-going edge of the clock. The active high asynchronous clear-direct and set-direct inputs are independent and override the J, K and clock inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
- Fully static operation
- Standardized symmetrical output characteristics
- Complies with JEDEC standard JESD 13-B
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 0 | ||
| Single-Ended | ||
| Gold | ||
| HEF4000 | ||
| 260 | ||
| -3.6 mA | ||
| 60@15V ns | ||
| 0.016 uA | ||
| 3 V | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 2 | ||
| 2 | ||
| 1 | ||
| 2 | ||
| 0 | ||
| -40 to 85 °C | ||
| Differential | ||
| 16SO | ||
| 16 | ||
| Inverting|Non-Inverting | ||
| 10 x 4 x 1.45 mm mm | ||
| 50 pF | ||
| No | ||
| Industrial | ||
| Set, Reset | ||
| SOIC | ||
| Positive-Edge | ||
| 3.3|5|9|12 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: