74LVT02D,118
NOR Gate, Quad, 2 Input, 14 Pins, SOIC, 74LVT02
- RoHS 10 Compliant
- Tariff Charges
The 74LVT02 is a quad 2-input NOR gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
- Wide supply voltage range from 2.7 V to 3.6 V
- Overvoltage tolerant inputs to 5.5 V
- BiCMOS high speed and output drive
- Direct interface with TTL levels
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
- Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM EIA/JESD22-A114-A exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- Specified from -40 °C to 85 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Gold | ||
| NOR | ||
| 260 | ||
| 2.8@3.3V ns | ||
| 2000 uA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 0 | ||
| -40 to 85 °C | ||
| 14SO | ||
| 14 | ||
| 8.75 x 4 x 1.45 mm | ||
| No | ||
| SOIC | ||
| 1000 uA |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |