74LVCH245APW,118

74LVCH245APW,118 is an 8bit bus transceiver with 3-state outputs. This device features an output enable and send/receive (DIR) for direction control. A HIGH on active-low OE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It complies with JEDEC standard (JESD8-7A (1.65V to 1.95V), JESD8-5A (2.3V to 2.7V), JESD8-C/JESD36 (2.7V to 3.6V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 3.6V
• CMOS low-power consumption, direct interface with TTL levels
• Overvoltage tolerant inputs to 5.5V, bus hold on all data inputs
• IOFF circuitry provides partial power-down mode operation, complies with JEDEC standard
• Input leakage current is ±0.1µA typ at (VI=5.5V or GND;VCC = 3.6V, Tamb = -40°C to +85°C)
• Supply current is 0.1µA typ at (VI=VCC or GND;IO = 0A;VCC = 3.6V, Tamb = -40°C to +85°C)
• Input capacitance is 4pF typ at (VCC = 0V to 3.6V;VI= GND to VCC, Tamb = -40°C to +85°C)
• Propagation delay is 6.5ns typ at (VCC = 1.65V to 1.95V, Tamb = -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSSOP20 package