74LVC8T245PW-Q100J

The 74LVC8T245-Q100 is a 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V. This flexibility makes the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range:
• High noise immunity
• Complies with JEDEC standards
• ESD protection:
  • MIL-STD-883, method 3015 Class 3A exceeds 4000 V
  • HBM JESD22-A114F Class 3A exceeds 4000 V
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ?)
• Maximum data rates:
  • 420 Mbps (3.3 V to 5.0 V translation)
  • 210 Mbps (translate to 3.3 V))
  • 140 Mbps (translate to 2.5 V)
  • 75 Mbps (translate to 1.8 V)
  • 60 Mbps (translate to 1.5 V)
• Suspend mode
  • Latch-up performance exceeds 100 mA per JESD 78B Class II
  • ±24 mA output drive (VCC = 3.0 V)
• Inputs accept voltages up to 5.5 V
• Low power consumption: 30 ?A maximum ICC
• IOFF circuitry provides partial Power-down mode operation
• Mu