74LVC32APW-Q100J
OR Gate, Quad, 2 Input, 14 Pins, TSSOP, 74LVC32A
- RoHS 10 Compliant
- Tariff Charges
The 74LVC32A provides four 2-input OR gates.. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.
- 5 V tolerant inputs for interfacing with 5 V logic
- Wide supply voltage range from 1.2 to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Complies with JEDEC standard:
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-B exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Gold over Nickel Palladium | ||
| OR | ||
| 260 | ||
| -24 mA | ||
| 24 mA | ||
| 2.5(Typ)@2.7V|2.2(Typ)@3.3V ns | ||
| 40 uA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 0 | ||
| -40 to 125 °C | ||
| 14TSSOP | ||
| 14 | ||
| 5.1(Max) x 4.4 x 0.95(Max) | ||
| No | ||
| Automotive | ||
| TSSOP | ||
| 0.1 uA |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |