74LVC1G74DP,125

74LVC1G74DP,125 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (active-low SD) and reset (active-low RD) inputs, and complementary Q and active-low Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

• Wide supply voltage range from 1.65V to 5.5V
• Overvoltage tolerant inputs to 5.5V, high noise immunity
• CMOS low power consumption, direct interface with TTL levels
• IOFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 250mA, complies with JEDEC standard
• Input leakage current is ±0.1µA typ at (VI=5.5V or GND;VCC = 0V to 5.5V, Tamb = -40°C to +85°C)
• Supply current is 0.1µA typ at (VI=5.5V or GND;VCC = 1.65V to 5.5V;IO = 0A, Tamb = -40°C to +85°C)
• Input capacitance is 4pF typical at (Tamb = -40°C to +85°C)
• Propagation delay is 6ns typical at (VCC = 1.65V to 1.95V, Tamb = -40°C to +85°C)
• Operating temperature range from -40°C to +125°C, TSSOP8 package