74LVC16373ADGG,112
Latch, 74LVC16373, D Type Transparent, Tri State Non Inverted, 5.5 ns, 24 mA, 48 Pins, TSSOP
The 74LVC16373 is a 16-bit D-type transparent latches featuring separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
- 5 V tolerant inputs/outputs for interfacing with 5 V logic
- Wide supply voltage range from 1.2 V to 3.6 V
- CMOS low power consumption
- Multibyte flow-through standard pinout architecture
- Multiple low inductance supply pins for minimum noise and ground bounce
- Direct interface with TTL levels
- All data inputs have bus hold (74LVCH16373A only)
- High-impedance when VCC =0V
- Complies with JEDEC standard:
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-B exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Transparent | ||
| Gold | ||
| LVC | ||
| 260 | ||
| -24 mA | ||
| 24 mA | ||
| 12@1.2V|3@3.3V ns | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 16 | ||
| 2 | ||
| 1 | ||
| 16 | ||
| 1 | ||
| 16 | ||
| 0 | ||
| -40 to 125 °C | ||
| 3-State | ||
| 48TSSOP | ||
| 48 | ||
| Non-Inverting | ||
| 12.6 x 6.2 x 1.05 mm | ||
| 50 pF | ||
| No | ||
| No | ||
| TSSOP | ||
| 5 V | ||
| D-Type |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Ships
in 1 bus. day