74LV4094PW,112

The 74LV4094 is a low voltage Si-gate CMOS device and is pin and functional compatible with 74HC4094; 74HCT4094. The 74LV4094 is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094 devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading 74LV4094 devices when the clock has a slow rise time.

• Optimized for low voltage applications: 1.0 V to 3.6 V
• Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
• Typical output ground bounce < 0.8 V at V_CC = 3.3 V and T_amb = 25 ?
• Typical HIGH-level output voltage (V_OH) undershoot: > 2 V at V_CC = 3.3 V and T_amb = 25 ?
• ESD protection:
  • HBM JESD22-A114E exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 ? to +85 ? and from -40 ? to +125 ?