74LV4051PW,112

The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). It is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC4051 and 74HCT4051. With E LOW, one of the eight switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are in the high-impedance OFF-state, independent of S0 to S2. VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E). The VCC to GND ranges are 1.0 V to 6.0 V. The analog inputs/outputs (Y0 to Y7, and Z) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).

• Optimized for low-voltage applications: 1.0 V to 6.0 V
• Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
• Low ON resistance:
  • 145 ? (typical) at V_CC - V_EE = 2.0 V
  • 80 ? (typical) at V_CC - V_EE = 3.0 V
  • 60 ? (typical) at V_CC - V_EE = 4.5 V
• Logic level translation:
  • To enable 3 V logic to communicate with ±3 V analog signals
• Typical ‘break before make’ built in
• ESD protection:
  • HBM JESD22-A114E exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 ? to +85 ? and from -40 ? to +125 ?