74LV393PW-Q100J
Counter/Divider Dual UP Counter 14-Pin TSSOP
The 74LV393 is a low–voltage Si-gate CMOS device and is pin and function compatible with 74HC393 and 74HCT393. The 74LV393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on nMR clears the counter stages and forces the outputs LOW, independent of the state of nCP.
- Optimized for low voltage applications: 1.0 V to 3.6 V
- Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
- Typical VOLP (output ground bounce) 0.8 V at VCC = 3.3 V; Tamb = 25 °C
- Typical VOHV (output VOH undershoot) 2 V at VCC = 3.3 V; Tamb = 25 °C
- Two 4-bit binary counters with individual clocks
- Divide-by any binary module up to 28 in one package
- Two master resets to clear each 4-bit counter individually
- Complies with JEDEC standard no. 7A
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Gold over Nickel Palladium | ||
| LV | ||
| Counter/Divider | ||
| 260 | ||
| 75(Typ)@1.2V|26(Typ)@2V|19(Typ)@2.7V|14(Typ)@3.3V ns | ||
| 0.16 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 1 | ||
| 4 | ||
| 2 | ||
| 0 | ||
| 4 | ||
| -40 to 125 °C | ||
| UP Counter | ||
| 14TSSOP | ||
| No | ||
| 14 | ||
| 5.1(Max) x 4.5(Max) x 0.95(Max) | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| Automotive | ||
| TSSOP | ||
| No | ||
| Negative-Edge | ||
| Binary | ||
| 3.3 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: