74LV14D,118
Inverter Schmitt Trigger, Hex, 1 Input, 14 Pins, SOIC, 74LV14
- RoHS 10 Compliant
- Tariff Charges
The 74LV14D is a low-voltage Si-gate CMOS device provides six Inverting buffers with Schmitt-trigger input. The device is pin and function compatible with 74HC14 and 74HCT14. The device is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.
- Optimized for low voltage applications (1 to 3.6V)
- Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
- 0.8V Output ground bounce
- 2V High-level output voltage (VOH) undershoot
- ESD protection - HBM JESD22-A114E exceeds 2000V, MM JESD22-A115-A exceeds 200V
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Schmitt Trigger | ||
| Gold | ||
| LV | ||
| Inverter Schmitt Trigger | ||
| 260 | ||
| -12 mA | ||
| 12 mA | ||
| 5.5 V | ||
| 80@1.2V|27@2V|20@2.7V|15@3.3V ns | ||
| 40 uA | ||
| 1 V | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 6 | ||
| -40 to 125 °C | ||
| Schmitt Trigger | ||
| 14SO | ||
| 14 | ||
| 8.75 x 4 x 1.45 mm | ||
| 50 pF | ||
| No | ||
| SOIC | ||
| 3.3 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |