74HCT4040D-Q100J
Counter, Binary Ripple, 74HCT, 79 MHz, Max Count 4095, 4.5 V to 5.5 V, 16 Pins, SOIC
The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
- Complies with JEDEC standard no. 7A
- Input levels:
- For 74HC4040: CMOS level
- For 74HCT4040: TTL level
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Gold over Nickel Palladium | ||
| HCT | ||
| Counter | ||
| 260 | ||
| 40@4.5V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 1 | ||
| 12 | ||
| 1 | ||
| 0 | ||
| 12 | ||
| -40 to 125 °C | ||
| UP Counter | ||
| 16SO | ||
| No | ||
| 16 | ||
| 10(Max) x 3.9 x 1.45(Max) | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| Automotive | ||
| SOIC | ||
| No | ||
| Negative-Edge | ||
| Binary | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: