74HCT4017D-Q100J
Counter/Divider Single UP Counter 16-Pin SOIC T/R
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9), an output from the most significant flip-flop, two clock inputs and an overriding asynchronous master reset input. The counter is advanced by either a LOW-to-HIGH transition at Clock Input while Clock Input is LOW or a HIGH-to-LOW transition at Clock Input while CP0 is HIGH. When cascading counters, the output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero independent of the clock inputs. Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
- Wide supply voltage range from 2.0 V to 6.0 V
- Input levels:
- For 74HC4017: CMOS level
- For 74HCT4017: TTL level
- Complies with JEDEC standard no. 7 A
- ESD protection:
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Gold over Nickel Palladium | ||
| HCT | ||
| Counter/Divider | ||
| 260 | ||
| 50@4.5V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 1 | ||
| 10 | ||
| 1 | ||
| 0 | ||
| 5 | ||
| -40 to 125 °C | ||
| UP Counter | ||
| 16SOIC | ||
| No | ||
| 16 | ||
| 10(Max) x 4(Max) x 1.45(Max) | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| Extended Industrial | ||
| SOIC | ||
| Yes | ||
| Positive-Edge/Negative-Edge | ||
| Decade | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |