74HCT377DB,118
Flip Flop, 74HCT377, D, 14 ns, 53 MHz, 4 mA, 20 Pins, SSOP
- RoHS 10 Compliant
- Tariff Charges
The 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable inputs. When data enable is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. Input data enable must be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
- Common clock and master reset
- Eight positive edge-triggered D-type flip-flops
- Complies with JEDEC standard no. 7A
- Input levels:
- For 74HC377: CMOS level
- For 74HCT377: TTL level
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V.
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Gold | ||
| HCT | ||
| D-Type Bus Interface | ||
| 260 | ||
| -4 mA | ||
| 32@4.5V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 8 | ||
| 8 | ||
| 8 | ||
| 1 | ||
| 0 | ||
| -40 to 125 °C | ||
| Single-Ended | ||
| 20SSOP | ||
| 20 | ||
| Non-Inverting | ||
| 7.4 x 5.4 x 1.8 mm | ||
| 50 pF | ||
| No | ||
| SSOP | ||
| Positive-Edge | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542330001 |
| Schedule B: | 8542330000 |