74HCT193PW,118

The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behaviour. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up and terminal count down outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause terminal count up to go LOW. terminal count up will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the terminal count down output will go LOW when the circuit is in the zero state and the CPD goes LOW.

• Input levels:
  • For 74HC193: CMOS level
  • For 74HCT193: TTL level
• Synchronous reversible 4-bit binary counting
• Asynchronous parallel load
• Asynchronous reset
• Expandable without external logic
• Complies with JEDEC standard no. 7A
• ESD protection:
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V.
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C