74HC75PW,118
Latch, 74HC75, Bistable, Transparent, Complementary, 19 ns, 5.2 mA, 16 Pins, TSSOP
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW.
- Complementary Q and Q outputs
- VCC and GND on the center pins
- Low-power dissipation
- Complies with JEDEC standard no. 7A
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- Multiple package options
- Specified from -40 °C to +80 °C and from -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Transparent | ||
| Gold | ||
| HC | ||
| 260 | ||
| -5.2 mA | ||
| 5.2 mA | ||
| 120@2V|24@4.5V|20@6V ns | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 4 | ||
| 2 | ||
| 1 | ||
| 4 | ||
| 0 | ||
| 4 | ||
| 0 | ||
| -40 to 125 °C | ||
| 16TSSOP | ||
| 16 | ||
| Inverting|Non-Inverting | ||
| 5.1 x 4.5 x 0.95 mm | ||
| 50 pF | ||
| No | ||
| No | ||
| TSSOP | ||
| D-Type |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: