74HC574PW,118
Flip Flop, 74HC574, D, 26 ns, 133 MHz, 7.8 mA, 20 Pins, TSSOP
-
RoHS 10 Compliant -
Tariff Charges
The 74HC574; 74HCT574 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC574; 74HCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74HC574; 74HCT574 is functionally identical to: 74HC564: but has non-inverting outputs 74HC374; 74HCT374: but has a different pin arrangement
- 3-state non-inverting outputs for bus oriented applications
- 8-bit positive, edge-triggered register
- Common 3-state output enable input
- ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Specified from -40 ? to +85 ? and from -40 ? to +125 ?
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Gold | ||
| HC | ||
| D-Type Bus Interface | ||
| 260 | ||
| -7.8 mA | ||
| 150@2V|30@4.5V|26@6V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 8 | ||
| 8 | ||
| 8 | ||
| 1 | ||
| 1 | ||
| -40 to 125 °C | ||
| Single-Ended | ||
| 3-State | ||
| 20TSSOP | ||
| 20 | ||
| Non-Inverting | ||
| 6.6 x 4.5 x 0.95 mm | ||
| 50 pF | ||
| No | ||
| TSSOP | ||
| Positive-Edge | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Ships
in 1 bus. day