74HC573PW-Q100,118

The 74HC573-Q100; 74HCT573-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC573-Q100; 74HCT573-Q100 has octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an output enable input are common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, i.e. a latch output changes state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When output enable is LOW, the contents of the 8 latches are available at the outputs. When output enable is HIGH, the outputs go to the high-impedance OFF-state. Operation of the output enable input does not affect the state of the latches. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Input levels:
  • For 74HC573-Q100: CMOS level
  • For 74HCT573-Q100: TTL level
• Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
• Useful as input or output port for microprocessors and microcomputers
• 3-state non-inverting outputs for bus-oriented applications
• Common 3-state output enable input
• Multiple package options
• ESD protection:
  • MIL-STD-883, method 3015 exceeds 2000 V
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ?)