74HC4094D,653

The 74HC4094D is an 8 stage shift and store bus register in 16 pin SOIC package. It is a 8bit serial in/serial or parallel out shift register with a storage register and 3 state outputs. Both shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on low to high transitions of CP input. Data is available at QS1 on LOW to HIGH transitions of CP input to allow cascading when clock edges are fast. The same data is available at QS2 on next HIGH to LOW transition of CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to storage register when STR input is high. Data in storage register appears at outputs whenever the output enable input (OE) is high. A low on OE causes the outputs to assume high impedance OFF state. Typical application includes serial to parallel data conversion and remote control holding register.

• Low-power dissipation
• CMOS Input level
• Complies with JEDEC standard No. 7A