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74HC40103D,653

Counter, Binary, Synchronous, Down, 74HC, 35 MHz, Max Count 255, 2 V to 6 V, 16 Pins, SOIC

Manufacturer:Nexperia
Product Category: Logic ICs, Counters
Avnet Manufacturer Part #: 74HC40103D,653
Secondary Manufacturer Part#: 74HC40103D,653
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the 40103 of the 4000B series. The 74HC40103 is specified in compliance with JEDEC standard no. 7A. The 74HC40103 consists of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. The 74HC40103 may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode.

  • Cascadable
  • Synchronous or asynchronous preset
  • Low-power dissipation
  • Complies with JEDEC standard no. 7A
  • ESD protection:
    • HBM EIA/JESD22-A114-B exceeds 2000 V
    • MM EIA/JESD22-A115-A exceeds 200 V.
  • Multiple package options
  • Specified from -40 °C to +80 °C and from -40 °C to +125 °C

Technical Attributes

Find Similar Parts

Description Value
Uni-Directional
Gold
HC
Counter
260
300@2V|60@4.5V|51@6V ns
0.008 mA
Surface Mount
MSL 1 - Unlimited
2
8
1
1
0
8
-40 to 125 °C
Down Counter
16SO
No
16
Synchronous|Asynchronous
10 x 4 x 1.45 mm
50 pF
No
Asynchronous
SOIC
Yes
Positive-Edge
Binary
5 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: EAR99
HTSN: 8542390050
Schedule B: 8542390060
In Stock :  0
Additional inventory
Factory Lead Time: 372 Weeks
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5000+
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20000+
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40000+
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