74HC393D-Q100J
Counter/Divider Dual 4-Bit Binary UP Counter 14-Pin SOIC T/R
The 74HC393-Q100; 7474HCT393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on nMR clears the counter stages and forces the outputs LOW, independent of the state of nCP. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
- Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
- Input levels:
- For 74HC393-Q100: CMOS level
- For 74HCT393-Q100: TTL level
- Complies with JEDEC standard no. 7A
- ESD protection:
- MIL-STD-883, method 3015 exceeds 2000 V
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 O)
- Two 4-bit binary counters with individual clocks
- Divide by any binary module up to 28 in one package
- Two master resets to clear each 4-bit counter individually
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Gold over Nickel Palladium | ||
| HC | ||
| Counter/Divider | ||
| 260 | ||
| 125@2V|25@4.5V|21@6V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 0 | ||
| 1 | ||
| 4 | ||
| 2 | ||
| 0 | ||
| 4 | ||
| -40 to 125 °C | ||
| UP Counter | ||
| 14SOIC | ||
| No | ||
| 14 | ||
| 8.75(Max) x 4(Max) x 1.45(Max) | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| Automotive | ||
| SOIC | ||
| No | ||
| Negative-Edge | ||
| Binary | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: