74HC273PW,118
Flip Flop, 74HC273, D, 26 ns, 122 MHz, 5.2 mA, 20 Pins, TSSOP
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Manufacturer:Nexperia
Product Category:
Logic ICs, Flip Flops
Avnet Manufacturer Part #: 74HC273PW,118
Secondary Manufacturer Part#: 74HC273PW,118
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RoHS 10 Compliant -
Tariff Charges
The 74HC273PW is an octal positive-edge triggered D-type Flip-flop features clock and master reset (MR\) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the low-to-high clock transition. A low on MR\ forces the outputs low independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
- Common clock and master reset
- CMOS Input levels
- Complies with JEDEC standard No. 7A
Technical Attributes
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| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Gold | ||
| HC | ||
| D-Type Bus Interface | ||
| 260 | ||
| -5.2 mA | ||
| 150@2V|30@4.5V|26@6V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 8 | ||
| 8 | ||
| 8 | ||
| 1 | ||
| 0 | ||
| -40 to 125 °C | ||
| Single-Ended | ||
| 20TSSOP | ||
| 20 | ||
| Non-Inverting | ||
| 6.6 x 4.5 x 0.95 mm | ||
| 50 pF | ||
| No | ||
| Master Reset | ||
| TSSOP | ||
| Positive-Edge | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: