74HC165PW,118

74HC165PW,118 is an 8bit parallel-in/serial out shift register. This device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and active-low Q7). When the parallel load input (active-low PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When active-low PL is HIGH data enters the register serially at DS. When the clock enable input (active-low CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on active-low CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. It features ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V).

• Wide supply voltage range from 2.0V to 6.0V
• CMOS low power dissipation, high noise immunity
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Asynchronous 8bit parallel load, synchronous serial input
• CMOS level input, complies with JEDEC standards
• Input leakage current is ±1µA maximum at (VI = VCC or GND; VCC = 6.0V)
• Supply current is 160µA maximum at (VI = VCC or GND; IO = 0A; VCC = 6.0V)
• Propagation delay is 250ns maximum at (VCC = 2.0V, -40°C to +125°C)
• Transition time is 110ns maximum at (VCC = 2.0V, -40°C to +125°C)
• Operating temperature range from -40°C to +125°C, TSSOP16 package