74HC165D-Q100,118

74HC165D-Q100,118 is an 8bit serial or parallel-in/serial-out shift register. This device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enables input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15V. This enables the device to be used in HIGH-to-LOW level shifting applications. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (grade 1) and is suitable for use in automotive applications. It is also used in Parallel-to-serial data conversion applications.

• Asynchronous 8bit parallel load, synchronous serial input
• Complies with JEDEC standard no. 7A, CMOS level input
• Supply voltage is 5V typical, input leakage current is ±0.1µA max at (VI = VCC or GND; VCC = 6V)
• Supply current is 8µA maximum at (VI = VCC or GND; IO = 0A; VCC = 6V)
• Input capacitance is 3.5pF typical at (25°C)
• Propagation delay is 52ns typical at (VCC = 2.0V, 25°C)
• Transition time is 19ns typical at (VCC = 2V, 25°C)
• Pulse width is 17ns typical at (VCC = 2.0V, 25°C)
• Maximum frequency is 17MHz typical at (VCC = 2.0V, 25°C)
• Operating temperature range from -40°C to +125°C, SO16 package