74HC161PW-Q100J
Shift Register Single 4-Bit Binary UP Counter 16-Pin TSSOP
The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for parallel enable are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET).
- Synchronous counting and loading
- Two count enable inputs for n-bit cascading
- Positive-edge triggered clock
- Asynchronous reset
- Output capability: standard
- ICC category: MSI
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Uni-Directional | ||
| Gold over Nickel Palladium | ||
| HC | ||
| Shift Register | ||
| 260 | ||
| 190@2V|38@4.5V|32@6V ns | ||
| 0.008 mA | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 1 | ||
| 4 | ||
| 4 | ||
| 1 | ||
| 0 | ||
| 4 | ||
| -40 to 125 °C | ||
| UP Counter | ||
| 16TSSOP | ||
| Yes | ||
| 16 | ||
| Synchronous | ||
| 5.1(Max) x 4.5(Max) x 0.95(Max) | ||
| 50 pF | ||
| No | ||
| Asynchronous | ||
| Automotive | ||
| TSSOP | ||
| Yes | ||
| Positive-Edge | ||
| Binary | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: