74CBTLV16211DGG;11

The 74CBTLV16211 provides a dual 12-bit high-speed bus switch with separate output enable inputs (1OE, 2OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is HIGH. To ensure the high-impedance OFF-state during power-up or power-down, 1OE and 2OE should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

• Supply voltage range from 2.3 V to 3.6 V
• High noise immunity
• Complies with JEDEC standard:
  • JESD8-5 (2.3 V to 2.7 V)
  • JESD8-B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM AEC-Q100-011 revision B exceeds 1000 V
• 5 O switch connection between two ports
• Rail to rail switching on data I/O ports
• CMOS low power consumption
• Latch-up performance exceeds 250 mA per JESD78B Class I level A
• I_OFF circuitry provides partial Power-down mode operation
• TSSOP56 packages: SOT364-1 and SOT481-2
• Specified from -40 °C to +85 °C and -40 °C to +125 °C