74AUP2G240DC,125

The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH.

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards:
  • JESD8-12 (0.8 V to 1.3 V)
  • JESD8-11 (0.9 V to 1.65 V)
  • JESD8-7 (1.2 V to 1.95 V)
  • JESD8-5 (1.8 V to 2.7 V)
  • JESD8-B (2.7 V to 3.6 V)
• ESD protection:
  • HBM JESD22-A114F Class 3A exceeds 5000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101E exceeds 1000 V
• Low static power consumption; I_CC = 0.9 µA (maximum)
• Latch-up performance exceeds 100 mA per JESD78 Class II
• Inputs accept voltages up to 3.6 V
• Low-noise overshoot and undershoot < 10 % of V_CC
• Input-disable feature allows floating input conditions
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from –40 ? to +85 ? and –40 ? to +125 ?