74AUP1Z125GM,115

The 74AUP1Z125 combines the functions of the 74AUP1GU04 and 74AUP1G125 with enable circuitry and an internal bias resistor to provide a device optimized for use in crystal oscillator applications. When not in use the EN input can be driven HIGH, pulling up the X1 input and putting the device in a low-power disable mode. Schmitt trigger action at the EN input makes the circuit tolerant to slower input rise and fall times across the entire Vcc range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using Ioff at output Y. The Ioff circuitry disables the output Y, preventing the damaging backflow current through the device when it is powered down. The integration of the two devices into the 74AUP1Z125 produces the benefits of a compact footprint, lower power dissipation and stable operation over a wide range of frequency and temperature.

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• ESD protection:
  • HBM JESD22-A114F Class 3A exceeds 5000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101E exceeds 1000 V
• Latch-up performance exceeds 100 mA per JESD78B Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of Vcc
• Ioff circuitry provides partial power-down mode operation at output Y
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C