74AUP1T34GW-Q100H

The 74AUP1T34 provides a single buffer with two separate supply voltages. Input A is designed to track VCC(A). Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y) accepts any supply voltage from 1.1 V to 3.6 V. This feature allows universal low voltage interfacing between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 1.1 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 1.1 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

• Wide supply voltage range from 1.1 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards:
  • JESD8-7 (1.2 V to 1.95 V)
  • JESD8-5 (1.8 V to 2.7 V)
  • JESD8-B (2.7 V to 3.6 V)
• ESD protection:
  • HBM JESD22-A114F Class 3A exceeds 5000 V
  • MM JESD22-A115-A exceeds 200 V
  • CDM JESD22-C101E exceeds 1000 V
• Wide supply voltage range:
  • V_CC(A) : 1.1 V to 3.6 V
  • V_CC(Y) : 1.1 V to 3.6 V
• Low static power consumption; I_CC = 0.9 µA (maximum)
• Each port operates over the full 1.1 V to 3.6 V power supply range
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of V_CC
• I_OFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and