74AUP1G240GN,132

<p>The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state.</p> <p>This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE is HIGH.</p> <p>Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.</p> <p>This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.</p> <p>This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.</p>

<ul><li>Wide supply voltage range from 0.8 V to 3.6 V</li><li>High noise immunity</li><li>Complies with JEDEC standards: <ul><li>JESD8-12 (0.8 V to 1.3 V)</li><li>JESD8-11 (0.9 V to 1.65 V)</li><li>JESD8-7 (1.2 V to 1.95 V)</li><li>JESD8-5 (1.8 V to 2.7 V)</li><li>JESD8-B (2.7 V to 3.6 V)</li></ul></li><li>ESD protection: <ul><li>HBM JESD22-A114F exceeds 5000 V</li><li>MM JESD22-A115-A exceeds 200 V</li><li>CDM JESD22-C101E exceeds 1000 V</li></ul></li><li>Low static power consumption; ICC = 0.9 µA (maximum)</li><li>Latch-up performance exceeds 100 mA per JESD 78 Class II</li><li>Inputs accept voltages up to 3.6 V</li><li>Low noise overshoot and undershoot < 10 % of VCC</li><li>Input-disable feature allows floating input conditions</li><li>IOFF c