74ALVCH16823DL,512

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (CP) input, an output-enableinput, a Master reset input and a clock-enable input are provided for each total 9-bit section. With the clock-enable input LOW, the D-type flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. Taking clock-enable HIGH disables the clock buffer, thus latching the outputs. Taking the Master reset (MR) input LOW causes all the Q outputs to go LOW independently of the clock. When output-enable is LOW, the contents of the flip-flops are available at the outputs. When the output-enable is HIGH, the outputs go to the high impedance OFF-state. Operation of the output-enable input does not affect the state of flip-flops. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• Multibyte flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins to minimize noise and ground bounce
• All data inputs have bus hold
• Output drive capability 50? transmission lines @ 85°C