74ALVCH16373DGG:11

The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs. One latch enable (LE) input and one output enable (OE) are provided per 8-bit section. The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, therefore a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the nDn inputs at a set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.

• Wide supply voltage range from 1.2 V to 3.6 V
• Complies with JEDEC standard JESD8-B
• CMOS low power consumption
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple V_CC and GND pins for minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold
• Output drive capability 50 ? transmission lines at 85 ?
• Current drive ±24 mA at V_CC = 3.0 V