74ALVC574PW,118
Flip Flop, 74ALVC574, D, 4.1 ns, 300 MHz, 24 mA, 20 Pins, TSSOP
- RoHS 10 Compliant
- Tariff Charges
The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin outputs enable is LOW, the contents of the eight flip-flops is available at the outputs. When pin outputs enable is HIGH, the outputs go to the high-impedance OFF-state. Operation of the outputs enable input does not affect the state of the flip-flops. The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin arrangement.
- Wide supply voltage range from 1.65 V to 3.6 V
- 3.6 V tolerant inputs/outputs
- CMOS low power consumption
- Direct interface with TTL levels (2.7 V to 3.6 V)
- Power-down mode
- Latch-up performance exceeds 250 mA
- Complies with JEDEC standards
- ESD protection
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Gold | ||
| ALVC | ||
| D-Type Bus Interface | ||
| 260 | ||
| -24 mA | ||
| 2.5@2.7V to 3.6V ns | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 8 | ||
| 8 | ||
| 8 | ||
| 1 | ||
| 1 | ||
| -40 to 85 °C | ||
| Single-Ended | ||
| 3-State | ||
| 20TSSOP | ||
| 20 | ||
| Non-Inverting | ||
| 6.6 x 4.5 x 0.95 mm | ||
| 50 pF | ||
| No | ||
| TSSOP | ||
| Positive-Edge | ||
| 1.8|2.5|3.3 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |