74AHCT374D,118
Flip Flop, 74AHCT374, D, 10.4 ns, 140 MHz, 8 mA, 20 Pins, SOIC
-
RoHS 10 Compliant -
Tariff Charges
The 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition. When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accept voltages higher than VCC
- Common 3-state output enable input
- Input levels:
- For 74AHCT374: TTL level
- ESD protection:
- HBM EIA/JESD22-A114E exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- CDM EIA/JESD22-C101C exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Gold | ||
| AHCT | ||
| D-Type Bus Interface | ||
| 260 | ||
| -8 mA | ||
| 10.4@4.5V to 5.5V ns | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 8 | ||
| 8 | ||
| 8 | ||
| 1 | ||
| 1 | ||
| -40 to 125 °C | ||
| Single-Ended | ||
| 3-State | ||
| 20SO | ||
| 20 | ||
| Non-Inverting | ||
| 13 x 7.6 x 2.45 mm | ||
| 50 pF | ||
| No | ||
| SOIC | ||
| Positive-Edge | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: