74AHCT257PW,118

The 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74AHCT257 is the logic implementation of a 4-pole 2-position switch, where the position of the switch is determined by the logic levels applied to input S. The outputs are forced to a high-impedance OFF-state when OE is HIGH.

• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Non-inverting data path
• Inputs accept voltages higher than VCC
• Input levels:
  • For 74AHCT257: TTL level
• ESD protection:
  • HBM EIA/JESD22-A114E exceeds 2000 V
  • MM EIA/JESD22-A115-A exceeds 200 V
  • CDM EIA/JESD22-C101C exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C