74AHCT126PW,118

<p>The 74AHC126-Q100; 74AHCT126-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.</p><p>The 74AHC126-Q100; 74AHCT126-Q100 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.</p><p>The 74AHC126-Q100; 74AHCT126-Q100 is identical to the 74AHC125-Q100; 74AHCT125-Q100 but has active HIGH output enable inputs.</p><p>This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.</p></p>

<ul><li>Automotive product qualification in accordance with AEC-Q100 (Grade 1)<ul><li>Specified from -40 °C to +85 °C and from -40 °C to +125 °C</li></ul></li><li>Balanced propagation delays</li><li>All inputs have Schmitt trigger action</li><li>Inputs accept voltages higher than V_CC</li><li>Input levels:<ul><li>For 74AHC126-Q100: CMOS level</li><li>For 74AHCT126-Q100: TTL level</li></ul></li><li>ESD protection:<ul><li>MIL-STD-883, method 3015 exceeds 2000 V</li><li>HBM JESD22-A114F exceeds 2000 V</li><li>MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 O)</li><li>Multiple package options</li></ul></li></ul>