74AHCT125PW-Q100,1
Buffer / Line Driver, 74AHCT125, 4 Element, 4.5 V to 5.5 V, 14 Pins, TSSOP
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RoHS 10 Compliant -
Tariff Charges
The 74AHC125-Q100; 74AHCT125-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC125-Q100; 74AHCT125-Q100 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74AHC125-Q100; 74AHCT125-Q100 is identical to the 74AHC126-Q100; 74AHCT126-Q100 but has active LOW enable inputs. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
- Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
- Balanced propagation delays
- All inputs have a Schmitt trigger action
- Inputs accept voltages higher than VCC
- For 74AHC125-Q100: CMOS input levels
- For 74AHCT125-Q100: TTL input levels
- ESD protection:
- MIL-STD-883, method 3015 exceeds 2000 V
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 O)
- Multiple package options
Technical Attributes
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| Description | Value | |
|---|---|---|
| No | ||
| Single-Ended | ||
| Gold | ||
| AHCT | ||
| Buffer/Line Driver | ||
| 260 | ||
| -8 mA | ||
| 8 mA | ||
| 5.5 V | ||
| 7.5@4.5V to 5.5V ns | ||
| 2 uA | ||
| 4.5 V | ||
| Surface Mount | ||
| MSL 1 - Unlimited | ||
| 4 | ||
| 4 | ||
| 0 | ||
| 4 | ||
| 4 Low | ||
| 4 | ||
| -40 to 125 °C | ||
| 3-State | ||
| 14 | ||
| Non-Inverting | ||
| 5.1 x 4.5 x 0.95 mm | ||
| 50 pF | ||
| No | ||
| TSSOP | ||
| 5 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390050 |
| Schedule B: | 8542390060 |
Factory Lead Time: