74AHCT123APW,118

<p>The 74AHC123A; 74AHCT123A are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.</p><p>The 74AHC123A; 74AHCT123A are dual retriggerable monostable multivibrators with output pulse width control by three methods. The basic pulse time is programmed by selection of an external resistor (REXT) and capacitor (CEXT).</p><p>Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering.</p><p>An internal connection from nRD to the input gate makes it possible to trigger the circuit by a positive-going signal at input nRD. The basic output pulse width is essentially determined by the value of the external timing components REXT and CEXT. When CEXT = 10 nF, the typical output pulse width is defined as: tW= REXT× CEXT where tW= pulse width in ns; REXT= external resistor in kO; CEXT= external capacitor in pF. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.</p></p>

<ul><li>All inputs have a Schmitt-trigger action</li><li>Inputs accept voltages higher than V_CC</li><li>DC triggered from active HIGH or active LOW inputs</li><li>Retriggerable for very long pulses up to 100 % duty factor</li><li>Direct reset terminates output pulse</li><li>For 74AHC123A only: operates with CMOS input levels</li><li>For 74AHCT123A only: operates with TTL input levels</li><li>ESD protection: <ul><li>HBM JESD22-A114E exceeds 2000 V</li><li>MM JESD22-A115-A exceeds 200 V</li><li>CDM JESD22-C101C exceeds 1000 V</li></ul></li><li>Multiple package options</li><li>Specified from -40 °C to +85 °C and from -40 °C to +125 °C</li></ul>