74AHC573BQ,115

<p>The 74AHC573-Q100; 74AHCT573-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.</p><p>The 74AHC573-Q100; 74AHCT573-Q100 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications.<p> A latch enable input (LE) and an output enable input (OE) are common to all latches.</p><p>When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.</p><p>When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.</p><p>This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.</p></p>

<ul><li>Automotive product qualification in accordance with AEC-Q100 (Grade 1)<ul><li>Specified from -40 °C to +85 °C and from -40 °C to +125 °C</li></ul></li><li>Balanced propagation delays</li><li>All inputs have a Schmitt trigger action</li><li>Common 3-state output enable input</li><li>Inputs accept voltages higher than V_CC</li><li>Input levels:<ul><li>For 74AHC573-Q100: CMOS input level</li><li>For 74AHCT573-Q100: TTL input level</li></ul></li><li>ESD protection:<ul><li>MIL-STD-883, method 3015 exceeds 2000 V</li><li>HBM JESD22-A114F exceeds 2000 V</li><li>MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 O)</li></ul></li><li>Multiple package options</li></ul>