74AHC374D,118

<p>The 74AHC374-Q100; 74AHCT374-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.</p><p>The 74AHC374-Q100; 74AHCT374-Q100 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.</p><p>A clock input (CP) and an output enable input (OE) are common to all flip-flops.</p><p>The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition.</p><p>When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.</p><p>This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.</p></p>

<ul><li>Automotive product qualification in accordance with AEC-Q100 (Grade 1)<ul><li>Specified from -40 °C to +85 °C and from -40 °C to +125 °C</li></ul></li><li>Balanced propagation delays</li><li>All inputs have Schmitt-trigger actions</li><li>Inputs accept voltages higher than V_CC</li><li>Common 3-state output enable input</li><li>Input levels:<ul><li>For 74AHC374-Q100: CMOS level</li><li>For 74AHCT374-Q100: TTL level</li></ul></li><li>ESD protection:<ul><li>MIL-STD-883, method 3015 exceeds 2000 V</li><li>HBM JESD22-A114F exceeds 2000 V</li><li>MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 O)</li></ul></li><li>Multiple package options</li></ul>