74AHC164PW,118

The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A LOW-level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.

Balanced propagation delays ¦ All inputs have Schmitt-trigger actions ¦ Inputs accept voltages higher than VCC ¦ Input levels: ? For 74AHC164: CMOS level ? For 74AHCT164: TTL level ¦ ESD protection: ? HBM EIA/JESD22-A114E exceeds 2000 V ? MM EIA/JESD22-A115-A exceeds 200 V ? CDM EIA/JESD22-C101C exceeds 1000 V ¦ Multiple package options ¦ Specified from -40 °C to +85 °C and from -40 °C to +125 °C