74ABT74PW,118

The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.

• Two 8-bit registered transceivers
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up reset
• Multiple V_CC and GND pins minimize switching noise
• Independent registers for A and B buses
• Output capability: +64 mA/-32 mA
• Latch-up protection exceeds 500 mA per Jedec JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model