PC28F256P33TFA

Micron's 65nm device is the latest generation of StrataFlash wireless memory featuring flexible, multiple-partition, dual-operation architecture. The device provides high-performance, asynchronous read mode and synchronous-burst read mode using 1.8V low-voltage, multilevel cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while PROGRAM and ERASE operations take place in the background. The multiple partitions allow flexibility for system designers to choose the size of the code and data segments.

• High-Performance Read, Program and Erase
  • 96 ns initial read access
  • 108 MHz with zero wait-state synchronous burst reads: 7 ns clock-to-data output
  • 133 MHz with zero wait-state synchronous burst reads: 5.5 ns clock-to-data output
  • 8-, 16-, and continuous-word synchronous-burst Reads
  • Programmable WAIT configuration
  • Customer-configurable output driver impedance
  • Buffered Programming: 2.0 µs/Word (typ), 512-Mbit 65 nm
  • Block Erase: 0.9 s per block (typ)
  • 20 µs (typ) program/erase suspend
• Architecture
  • 16-bit wide data bus
  • Multi-Level Cell Technology
  • Symmetrically-Blocked Array Architecture
  • 256-Kbyte Erase Blocks
  • 1-Gbit device: Eight 128-Mbit partitions
  • 512-Mbit device: Eight 64-Mbit partitions
  • 256-Mbit device: Eight 32-Mbit partitions
  • 128-Mbit device: Eight 16-Mbit partitions
  • Read-While-Program and Read-While-Erase
  • St